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- Each team must have 2 to 4 members. Intercollege members are allowed.
- Hackathon duration: 24 uninterrupted hours.
- At least one team member must stay overnight at the venue.
- Bring your own laptop, charger, extension cord, and accessories.
- Use Verilog, VHDL, SystemVerilog, FPGA platforms, and approved EDA tools.
- Projects must have a working design with simulation and verification results.
- FPGA implementation is encouraged but not mandatory.
- Teams must explain their design, architecture, verification, and results.
- Final presentation using the provided PPT template is mandatory.
- Plagiarism or copied projects will lead to disqualification.
- Open-source resources must be properly credited.
- Submit all deliverables before the deadline.
- Follow professional conduct throughout the event.
- Jury decisions will be final.
💡 Open Innovation
You can also bring your own project idea from this track. No problem statement needed — just build something amazing!
View Problem Statements
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